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INTEGRATED CIRCUITS
DATA SHEET
SAA5250 Interface for data acquisition and control (for multi-standard teletext systems)
Product specification File under Integrated Circuits, IC02 January 1987
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
GENERAL DESCRIPTION
SAA5250
The SAA5250 is a CMOS Interface for Data Acquisition and Control (CIDAC) designed for use in conjunction with the Video Input Processor (SAA5230) in a multi-standard teletext decoder. The device retrieves data from a user selected channel (channel demultiplexer), as well as providing control signals and consecutive addressing space necessary to drive a 2 K bytes buffer memory. The system operates in accordance with the following transmission standards: * French Didon Antiope specification D2 A4-2 (DIDON) * North American Broadcast Teletext specification (NABTS) * U.K. teletext (CEEFAX) Features * 7,5 MHz maximum conversion rate * Three prefixes; DIDON, NABTS and U.K. teletext (CEEFAX) * Mode without prefix * Internal calculation of the validation (VAL) and colour burst blanking (CBB) signals, if programmed * Programmable framing code and channel numbers * Error parity calculation or not (odd parity) * Hamming processing of the prefix byte * Full channel or VBI reception * Slow/fast mode (detection of page flags or not) * Maximum/default format up to 63 bytes * Addressing space of 2 K bytes of the static memory * Multiplexed address/data information is compatible with Motorola or Intel microcontrollers * CIDAC is `MOTEL' compatible PACKAGE OUTLINES SAA5250P: 40-lead DIL; plastic (SOT129); SOT129-1; 1996 December 02. SAA5250T: 40-lead mini-pack; plastic (VSO40); SOT158-1; 1996 December 02.
January 1987
2
k, full pagewidth
January 1987
PAGE DETECTION 9-16 SEQUENCE CONTROLLER CHANNEL COMPARATOR 17 HAMMING CORRECTOR 18 INTERFACE 21 19 ALE CS RD WR PROGRAM REGISTER 8 DB7 to DB0 REGISTER
Philips Semiconductors
FRAMING CODE DETECTION
SD
6
SERIAL REGISTER
PARALLEL REGISTER
SERIAL/PARALLEL CONVERTER
Interface for data acquisition and control (for multi-standard teletext systems)
DCK FORMAT TRANSCODER 2 K BYTE FIFO MEMORY CONTROLLER
5
3
SAA5250
FORMAT COUNTER MEMORY INTERFACE 11 7 8 1, 39-30 8 29-22 40 20 MS WE A10 to A0 D7 to D0 VDD VSS
CLOCK GENERATION
FORMAT PROCESSOR
VAL IN/ SYNC
3
VAL OUT
2
CBB
4
VALIDATION SIGNAL PROCESSING
MGH075
Product specification
SAA5250
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, halfpage
A10 VAL OUT
1 2
40 V
DD
39 A9 38 A8 37 A7 36 A6 35 A5 34 A4 33 A3 32 A2 31 A1
VAL IN/ 3 SYNC CBB DCK SD MS WE DB7 4 5 6 7 8 9
DB6 10 DB5 11 DB4 12 DB3 13 DB2 14 DB1 15 DB0 16 ALE 17 CS 18 WR 19 V SS 20
MGH074
SAA5250
30 A0 29 D7 28 D6 27 D5 26 D4 25 D3 24 D2 23 D1 22 D0 21 RD
Fig.2 Pinning diagram.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
PINNING FUNCTION MNEMONIC A10 and A0 to A9 VAL OUT VAL IN/SYNC CBB DCK SD MS WE DB7 to DB0 ALE CE WR VSS RD D0 to D7 VDD PIN NO. 1 and 30 to 39 2 3 4 5 6 7 8 9 to 16 17 18 19 20 21 22 to 29 40 FUNCTION
SAA5250
Memory address outputs used by CIDAC to address a 2 K byte buffer memory Validation output signal used to control the location of the window for the framing code. Validation input signal (line signal) used to give or calculate a window for the framing code detection Colour burst blanking output signal used by the SAA5230 as a data slicer reset pulse Data clock input, in synchronization with the serial data signal Serial data input, arriving from the demodulator Chip enable output signal for buffer memory selection Write command output for the buffer memory 8-bit three state input/output data/address bus used to transfer commands, data and status between the CIDAC registers and the CPU Demultiplexing input signal for the CPU data bus Chip enable input for the SAA5250 Write command input (when LOW) ground Read command input (when LOW) 8-bit three state input/output data bus used to transfer data between CIDAC and the buffer memory +5 V power supply
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
FUNCTIONAL DESCRIPTION Microcontroller interface
SAA5250
The microcontroller interface communicates with the CPU via the handshake signals DB7 - DB0, ALE, CS, RD, WR. The microcontroller interface produces control commands as well as programming the registers to write their contents or read incoming status/data information from the buffer memory. The details of the codes used to address the registers are given in Table 2. The CIDAC is `MOTEL' compatible (MOTEL compatible means it is compatible with standard Motorola or Intel microcontrollers). It automatically recognizes the microcontroller type (such as the 6801 or 8501) by using the ALE signal to latch the state of the RD input. No external logic is required. Table 1 Recognition signals CIDAC ALE RD WR Table 2 CIDAC register addressing CODES R 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 W 0 0 0 0 0 0 0 0 0 0 0 0 CS 0 0 0 0 1 1 1 1 0 0 0 0 DB2 0 0 1 1 0 0 1 1 0 0 1 1 DB1 0 1 0 1 0 1 0 1 0 1 0 1 DB0 FUNCTION write register R0 write register R1 write register R2 write register R3 write register R4 write register R5 write command register R6 (initialization command) write register R7 read status read data register test (not used) test (not used) ALE RD WR 8049/8051 TIMING 1 AS DS, E, 2 R/W 6801/6805 TIMING 2
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Register organization
SAA5250
R0 register
Table 3 R0 Register contents R04 SLOW/FAST MODE 0 = slow mode 1 = fast mode R03 PARITY 0 = no parity control 1 = odd parity R02 TO R00 USED PREFIXES 000 = DIDON long 001 = DIDON medium 010 = DIDON short 011 = not used 100 = U.K. teletext 101 = NABTS 110 = without prefix 111 = without prefix
handbook, full pagewidth
CEEFAX
FC MRAG A format
magazine and row address group
DIDON short
FC
A1 DIDON medium FC
A2
A1 DIDON long FC
A2
A3
CI
format
A1 NABTS FC
A2
A3
CI
PS
MGH077
Fig.3 Five prefixes.
All of the bytes (see Fig.3) are Hamming protected. The hatched bytes are always stored in the memory in order to be processed by the CPU (see section `Prefix processing'). In the mode without prefix all of the bytes which follow the framing code are stored in the memory until the end of the data packet, the format is then determined by the contents of the R3 register. If R03 = 0; no parity control is carried out and the 8-bits of the incoming data bytes are stored in the fifo memory. If R03 = 1; the 8th bit of the bytes following the prefix (data bytes) represents the result of the odd parity control. If R04 = 0; the device operates in the slow mode. The CIDAC retrieves data from the user selected magazine (see section `R1 and R2') and without searching for a start to a page stores the data into the FIFO memory.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
If R04 = 1; the device operates in the fast mode. Prior to writing into the FIFO memory, the CIDAC searches for a start to a page which is variable due to the different prefixes: * DIDON (long, medium and short): using the redundant bytes, SOH RS, X RS and SOH X (where X is a bit affected by a parity error) * NABTS, the least significant bit of the PS byte is set to 1 * U.K. teletext, ROW = 0
R1 register
Table 4 R1 Register contents R16 TO R14 FORMAT TABLE (1) 000 = list 1 001 = list 2 010 = list 3 011 = list 4 1XX = maximum/default value used (R3) Note 1. X = don't care If VAL IN/SYNC = 1; the line signal immediately produces a validation signal for the framing code detection. If VAL OUT = 0; the line signal is used as a starting signal for an internally processed validation signal (see Fig.15). The framing code window width is fixed at 13 clock periods and the delay is determined by the contents of the R5 register (R56 to R50). At any moment the user is able to ensure that the framing code window is correctly located. This is accomplished by the VAL OUT pin reflecting the internal validation signal. A CBB signal with programmable width (see section `R7 register') can also be generated, this is used as a data slicer reset pulse by the SAA5230. The line signal is used as the starting point of the internal CBB signal width fixed by the contents of the R7 register. If R16 = 0; then bits R15 and R14 provide the format table number using DIDON long and short prefixes (see Table 6). If R16 = 1; then the format is determined by the contents of the R3 register. The bits R13 to R10 represent the first channel number to be checked in the prefix. In U.K. teletext mode only 3 bits are required, so R13 = X. R13 TO R10 CHANNEL NUMBERS (FIRST DIGIT) first digit hexadecimal value
R17 VAL IN/SYNC 1 = VAL 0 = SYNC
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Table 5 Format table FORMAT BYTE B8, B6, B4 AND B2 (1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note 1. B8 = MSB and B2 = LSB. LIST 1 0 1 2 3 4 8 12 16 20 24 28 32 36 40 44 48 LIST 2 0 1 2 3 5 9 13 17 21 25 29 33 37 41 45 49 LIST 3 0 1 2 3 6 10 14 18 22 26 30 34 38 42 46 50
SAA5250
LIST 4 0 1 2 3 7 11 15 19 23 27 31 35 39 43 47 51
R2 register
Table 6 R2 Register contents R27 TO R24 channel number, third digit (hexadecimal value, third digit) Note 1. R27 and R23 = MSB and R24 and R20 = LSB The R2 register provides the other two parts of the channel number (depending on the prefix) that require checking. R23 TO R20 channel number, second digit (hexadecimal value, second digit
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
R3 register
Table 7 R3 register contents R35 TO R30 6-BIT FORMAT MAXIMUM/DEFAULT VALUE 000000 = 0 000001 = 1 - - - 111111 = 63 This 6-bit byte gives:
SAA5250
* In the DIDON long and short mode, a maximum format in case of corrupted transmission (multiple errors on the Hamming corrector) * A possible 63-bit format for all types of prefix
R4 register
Table 8 R4 register contents R47 TO R40 8-bit register used for storing the framing code value which will be compared with the third byte of each data line
R5 register
Table 9 R5 register contents R57 NEGATIVE/POSITIVE 0 = negative edge for sync signal 1 = positive edge for sync signal Note 1. F = data clock acquisition frequency (DCK). Using R57 it is possible to start the internal synchronization delay (tDVAL) on the positive or negative edge. R56 TO R50 SYNCHRONIZATION DELAY 7-bit sync delay, giving a maximum delay of (27 - 1) x 106 s/F (Hz)
R6 write command register
This is a fictitious register. Only the address code (see Table 2) is required to reset the CIDAC. See Table 11 for the status of the FIFO memory on receipt of this command.
R7 register
Table 10 R7 register contents R75 TO R70 6-bit register used to give a maximum colour burst blanking signal of: (26 - 1) x 106 s/F (Hz) Note 1. F = data clock acquisition frequency.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Fifo status register (read R0 register)
Table 11 Fifo register contents DB2 TO DB0 DB2 = 1 memory empty DB1 = 1, data not present in the read data register
SAA5250
DB0 = 0 memory not full
Once the relevant prefix and the right working modes have been given by the corresponding registers, a write command to the R6 register enables the CIDAC to accept and process serial data. Channel comparator This is a four bit comparator which compares the three user hexadecimal defined values in R1 and R2 to corresponding bytes of the prefix coming from the Hamming corrector. If the three bytes match, the internal process of the prefix continues. If they do not match the CIDAC returns to a wait state until the next broadcast data package is received. FIFO memory controller The FIFO memory contains all the necessary functions required for the control of the 11-bit address memory (2 K byte). The functions contained in the FIFO memory are as follows: * write address register (11-bits) * read address register (11-bits) * memory pointer (11-bits) * address multiplexer (11-bits) * write data register (8-bits) * read data register (8-bits) * data multiplexer * control logic The FIFO memory provides the memory interface with the following: * 11-bit address bus (A10 to A0) * 8-bit data bus (D7 to D0) * two control signals, memory select (MS) and write enable (WE)
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Operation
SAA5250
The CIDAC uses the same clock signal for data acquisition and internal processing, this allows the CIDAC to have a write and a read cycle during each character period (see Fig.13). The first half of the character period is a write cycle and the second half is a read cycle. Consequently, for an 8 MHz bit rate the maximum memory cycle time is 500 ns. When the first data byte is written into the FIFO memory, thus transferred into the read register, the FIFO memory enters the status shown in Table 12. Table 12 FIFO status DB2 TO DB0 DB2 = 1 memory empty When the FIFO memory is full two events occur: * the write address register points to the next address after the last written address * when new data is to be written, the memory select signal output ceases Memory interface The memory interface contains all the buffers for the memory signals mentioned in the section `FIFO memory controller'. Page detection This part of the CIDAC contains a parallel register with logic which detects (only in fast mode) a start of a page or data group (see section `R0 register'). Hamming correction (see Tables 13 and 14) The Hamming correction provides (see section `Prefix processing'): * hexadecimal value of the Hamming code * accept/reject code signal * parity information DB1 = 0 data available DB0 = 0 memory not full
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Table 13 Hamming correction (coding) HEXADECIMAL NOTATION 0 1 2 3 4 5 6 7 8 9 A B C D E F Note 1. B7 = B8 B6 B4 B5 = B6 B4 B2 B3 = B4 B2 B8 B1 = B2 B8 B6 = exclusive OR gate function B8, B6, B4 and B2 = data bits B7, B5, B3 and B1 = redundancy bits B8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B7 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 B6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B5 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 B4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B3 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0
SAA5250
B2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
B1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Table 14 Hamming correction (decoding) A 1 0 1 0 1 1 1 0 0 B 1 0 1 1 1 0 0 0 1 A.B.C = 0 Note 1. A = B8 B6 B2 B1 B = B8 B4 B3 B2 C = B6 B5 B4 B2 D = B8 B7 B6 B5 B4 B3 B2 B1 = exclusive OR gate function C 1 1 1 0 0 0 1 0 1 D 1 0 0 0 0 0 0 0 0 1 INTERPRETATION no error error on B8 error on B7 error on B6 error on B5 error on B4 error on B3 error on B2 error on B1 multiple errors
SAA5250
INFORMATION accepted corrected accepted corrected accepted corrected accepted corrected accepted rejected
Format processing The format processing consist of two parts:
part 1
A format transcoder produces a 6-bit code (up to 63) and uses the following as inputs: * DIDON long and short prefixes; hamming corrected code (4-bits) accept/reject code condition table number (see section `R1 register', bits R15 and R14) * Other prefixes (R16 = 1) * 6-bit maximum/default format (see section `R3 register')
part 2
A format counter operating at the character clock frequency which receives the 6-bit code from the format transcoder and is used to check the data packet length following the prefix. Serial/parallel converter The serial/parallel converter consists of three parts: * An 8-bit shift register which receives the SD input and operates at the bit frequency (DCK). * An 8-bit parallel register used for storage. * A framing code detection circuit. This logic circuit compares the 8-bits of the R4 register with that of the serial register. If seven bits out of eight match (in coincidence with a validation window), it produces a start signal for a new teletext data line to the sequence controller. January 1987 14
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Clock generation The clock generator does the following: * acts as a buffer for the DCK clock * generates the character clock
SAA5250
As soon as a framing code has been detected, a divide by 8 counter is initialized and the character clock is started. The clock drives the following: * sequence controller * parallel registers * format counter Processing of VAL and CBB signals The circuit has one input (VAL IN/SYNC) and two outputs (VAL OUT and CBB). The circuit consists of: * 7-bit counter operating at DCK frequency which produces the framing code validation pulse delay * 7-bit comparator which compares the contents of the R5 register (bits R56 to R50) to the bit counter * a 6-bit counter operating at DCK frequency which produces the CBB pulse width * 6-bit comparator which compares the contents of the R7 register (bits R75 to R70) to the bit counter * control logic required to provide the start condition for the VAL signal and the CBB pulse width (on the negative or positive edge of the sync signal) The CBB signal useful occurs when the associated video processor: * has no sandcastle pulse to send back to the demodulator * carries out the synchronization of the time base clock. In this event the CBB acts as a data slicer reset pulse The VAL OUT is a control signal which reflects the internal framing code window. Prefix processing (see Table 21) Figs 4 to 9 show the acquisition flow charts for each prefix type coded in the R0 register (bits R02 to R00). As soon as an initialization command is received by the CIDAC, a write command to the R6 register (only the address is significant), is ready to receive data from a dedicated channel number and store the data in the FIFO memory (explained in the following paragraphs, each paragraph being dedicated to an individual type of prefix). DIDON long (see Fig.4) In this mode, the continuity index, format and data bytes are written into the FIFO memory. (In fast mode, information can be written into the FIFO memory only after a page detection.)
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Table 15 Continuity index processing result D7 A/R D6 X D5 X D4 X D3 CI3 D2 CI2 D1 CI1 D0 CI0
SAA5250
Table 16 Format processing result D7 A/R Note 1. A/R = 0, if rejected 2. A/R = 1, if accepted 3. X = don't care DIDON mediun (see Fig.5) Only data bytes are written into the FIFO memory. (In fast mode, information can be written into the FIFO memory only after a page detection.) DIDON short (see Fig.6) In this mode, format and data bytes are written into the FIFO memory. (In fast mode, information can be written into the FIFIFO memory only after a page detection.) Table 17 Format processing result D7 A/R D6 X D5 F5 D4 F4 D3 F3 D2 F2 D1 F1 D0 F0 D6 X D5 F5 D4 F4 D3 F3 D2 F2 D1 F1 D0 F0
NABTS (see Fig.7) In this mode, the continuity index, packet structure and data bytes are written into the FIFO memory. (In fast mode, information can be written into the FIFO memory only after a page detection.) Table 18 Continuity index processing result D7 A/R D6 X D5 X D4 X D3 CI3 D2 CI2 D1 CI1 D0 CI0
Table 19 Packet structure processing result D7 A/R D6 X D5 X D4 X D3 PS3 D2 PS2 D1 PS1 D0 PS0
U.K. teletext (see Fig.8) In this mode, the magazine and row address group (two bytes) and data bytes are written into the FIFO memory. (In fast mode, information can be written into the FIFO memory only after a flag detection.)
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
Table 20 Magazine and row address group processing results D7 A/R D6 X D5 X D4 RW4 D3 RW3 D2 RW2 D1 RW1 D0 RW0
SAA5250
Without prefix All the data following the framing code are stored in the FIFO memory. Table 21 Prefix processing PREFIXES DIDON long DIDON medium DIDON short NABTS U.K. teletext without prefix Note 1. after page/flag detection 2. A1, A2, A3 are channel numbers CI = continuity index F = format PS = packet structure D = data MRAG = magazine and row address group CONSTRUCTION OF PREFIXES A1, A2, A3, CI, F and D A1, A2 and D A1, F and D A1, A2, A3 CI, PS and D MRAG and D BYTES STORED IN FIFO MEMORY DURING SLOW MODE CI, F and D D F and D CI, PS and D MRAG and D BYTES STORED IN FIFO MEMORY DURING FAST MODE CI(1) , F(1) and D(1) D(1) F(1) and D(1) CI(1), PS(1) and D(1) MRAG(1) and D(1)
all bytes of the data packet following the framing code are written into the FIFO memory
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
Fig.4 DIDON (long) acquisition flow chart.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING CODE DETECT
0
1 A1 O.K. 0
1 A2 O.K. 0
1 LOAD FORMAT COUNTER WITH EXPLICIT VALUE
FORMAT COUNTER = 0
1
0 FAST SLOW/FAST MODE
PAGE IN PROGRESS
1
SLOW
0 DECREMENT FORMAT COUNTER 1 0 START OF PAGE DETECT
SET PAGE IN PROGRESS FLAG
DECREMENT FORMAT COUNTER. WRITE DATA BYTES INTO FIFO
MGH084
Fig.5 DIDON (medium) acquisition flow chart.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING CODE DETECT
0
1 A O.K. 0
1 LOAD FORMAT COUNTER WITH INCOMING VALUE
FAST
SLOW/FAST MODE
PAGE IN PROGRESS 0
1
SLOW
1
FORMAT COUNTER = 0
0 DECREMENT FORMAT COUNTER
START OF PAGE DETECT
0
1 SET PAGE IN PROGRESS FLAG
WRITE FORMAT INTO FIFO
FORMAT COUNTER = 0
1
0 DECREMENT FORMAT COUNTER. WRITE DATA BYTES INTO FIFO
MGH083
Fig.6 DIDON (short) acquisition flow chart.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING CODE DETECT
0
1 A1 O.K. 0
1 A2 O.K. 0
1 A3 O.K. 0
1 SAVE CI BYTES
LOAD FORMAT COUNTER WITH IMPLICIT FORMAT
FAST
SLOW/FAST MODE
DATA GROUP IN PROGRESS
1
SLOW
0 0 SYNCHRONIZING PACKET 1 SET DATA GROUP IN PROGRESS FLAG
WRITE CI BYTE INTO FIFO
WRITE PS BYTE INTO FIFO
FORMAT COUNTER = 0
1
0 DECREMENT FORMAT COUNTER. WRITE DATA BYTES INTO FIFO
MGH082
Fig.7 NABTS acquisition flow chart.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
INITIALIZE CIDAC
FRAMING CODE DETECT
0
1 MAG O.K. 0
1 SLOW/FAST MODE PAGE IN PROGRESS 1
SLOW
0 0 ROW 0
SET PAGE IN PROGRESS FLAG
WRITE ROW NUMBER INTO FIFO LOAD FORMAT COUNTER WITH IMPLICIT FORMAT
FORMAT COUNTER = 0
DECREMENT FORMAT COUNTER. WRITE DATA BYTES INTO FIFO
MGH081
Fig.8 U.K. teletext acquisition flow chart.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, halfpage
INITIALIZE CIDAC
FRAMING CODE DETECT
0
1 LOAD FORMAT COUNTER WITH EXPLICIT FORMAT
FORMAT COUNTER = 0
1
0 DECREMENT FORMAT COUNTER. WRITE DATA BYTES INTO FIFO
MGH080
Fig.9 Without prefix acquisition chart.
handbook, full pagewidth
DCK
5 D
clock input to data acquisition circuit
SD
6
data input to data acquisition circuit
D
CBI D = clamping diodes CBI = clamping pulse, the pulse width is given by the R7 register
MGH076
Fig.10 SD and DCK input circuitry.
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) PARAMETER Supply voltage range Input voltage range Total power dissipation Operating ambient temperature range Storage temperature range CONDITIONS SYMBOL VDD VI Ptot Tamb Tstg MIN. -0,3 -0,3 - 0 -20 6,5 VDD+0,3 400 70 +125 MAX.
SAA5250
UNIT V V mW C C
D.C. CHARACTERISTICS (except SD and DCK) VDD = 5 V10%; VSS = 0 V; Tamb = 0 to 70 C, unless otherwise specified PARAMETER Supply voltage range Input voltage HIGH Input voltage LOW Input leakage current Output voltage HIGH Output voltage LOW Iload = 1 mA Iload = 4 mA, at pins 9 to 16 and 22 to 29 Iload = 1 mA all other outputs Power dissipation Input capacitance CONDITIONS SYMBOL VDD VIH VIL II VOH 4,5 2 - - VDD-0,4 MIN. 5,0 - - - - TYP. 5,5 VDD 0,8 1,0 - MAX. V V V A V UNIT
VOL VOL P CI
- - - -
- - 5 -
0,4 0,4 - 7,5
V V mW pF
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SD and DCK D.C. CHARACTERISTICS (see Fig.10) VDD = 5 V; VSS = 0 V; Tamb = 0 to 70 C, unless otherwise specified PARAMETER DCK Input voltage range (peak-to-peak value) Input current Input capacitance External coupling capacitor SD D.C. input voltage range HIGH note 1 D.C. input voltage range LOW note 2 A.C. input voltage (peak-to-peak value) Input leakage current Input capacitance External coupling capacitor VI = 0 to VDD VIH VIL VI(p-p) II CI Cext 2,0 - 2,0 - - 10 - - - - - - - 0,8 - 10 30 - VI = 0 to VDD VI(p-p) II CI Ctext 2,0 5 - 10 - - - - - 200 30 - CONDITIONS SYMBOL MIN. TYP. MAX.
SAA5250
UNIT
V A pF nF
V V V A pF nF
January 1987
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Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
A.C. CHARACTERISTICS VDD = 5 V 10%; Reference levels for all inputs and outputs, VIH = 2 V; VIL = 0,8 V; VOH = 2,4 V; VOL = 0,4 V; CL = 50 pF on DB7 to DB0; Tamb = 0 to 70 = C, unless otherwise specified PARAMETER Microcontroller interface Cycle time Address pulse width RD HIGH or WR to ALE HIGH Fig.11 DS LOW to AS HIGH ALE LOW to RD LOW or WR LOW AS LOW to DS HIGH Write pulse width Address and chip select set-up time Address and chip select hold time Read to data out period Data hold after RD R/W to DS set-up time R/W to DS hold time Data set-up time Data hold time Read pulse width Memory interface WE LOW to DCK falling edge WE HIGH to DCK falling edge MS LOW to DCK rising edge MS HIGH to DCK rising edge Address output from DCK rising edge Data output from WE falling edge Data hold from WE rising edge Address set-up time to data WE pulse width MS pulse width note 4 note 5 note 6 Fig.12 Fig.12 write cycle write cycle note 3 Fig.13 tWEL tWEH tMSL tMSH tAV tDWL tDWH tAD tWEW tMSW 10 10 10 10 10 0 0 - 3 x DCK 2 x DCK - - - - - - - - - - 80 80 80 85 120 10 - 3 x DCK -110 - - ns ns ns ns ns ns ns ns ns ns Fig.12 Fig.11 Fig.12 CONDITIONS Figs 11 and 12 tCY tLHLL tAHRD tAHRD tALRD tALRD tWL tASL tAHL tRD tDR tRWS tRWH tDW tWD tRL 400 50 0 0 30 30 120 10 20 - 10 40 10 50 10 150 or DCK + 50 - - - - - - - - - - - - - - - - - - - - - - - - - 130 100 - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. UNIT
January 1987
26
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
PARAMETER Demodulator interface (see SD and DCK D.C. CHARACTERISTICS) DCK LOW DCK HIGH Serial data set-up time Serial data hold time Validation signal set-up time Validation signal hold time Other I/O signals User definable width as a multiple of DCK period Validation signal width User definable delay as a multiple of DCK period Notes to the characteristics 1. Unless R7 = 00 the value given is unacceptable. note 7 Fig.15 tWCBB tWVAL tDVAL 0 X 0 - 12 - 63 X 127 Fig.14 conversion rate < 7,5 MHz conversion rate < 7,5 MHz tDCKL tDCKH tSSD tHSD tSVALI tHVALI 55 55 0 30 50 50 - - - - - - - - - - - - CONDITIONS SYMBOL MIN. TYP.
SAA5250
MAX.
UNIT
ns ns ns ns ns ns
DCK DCK DCK
2. When CBI signal is maintained at 0 V (R7 = 00) and if SD input signal is correctly referenced to ground, no coupling capacitor is required. 3. DCK + 50 is the DCK period plus 50 ns. 4. 3 x DCK - 110 is 3 x DCK period - 110 ns. 5. 3 x DCK is 3 x DCK period. 6. 2 x DCK is 2 x DCK period. 7. X = irrelevant.
January 1987
27
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
READ handbook, full pagewidth CYCLE
tCY
ALE tLHLL tRL
tAHRD RD
tALRD
WR
CS tAHL
tASL BUS ADDRESS
tRD
tDR D OUT
WRITE CYCLE tCY
ALE tLHLL tWL
tAHRD WR tAHRD RD
tALRD
CS tAHL tWD
tASL BUS ADDRESS
tDW D IN
MGH087
Fig.11 Timing diagram for microcontroller interface (Intel).
January 1987
28
January 1987
tCY tALRD tAHRD tLHLL
(1)
Philips Semiconductors
handbook, full pagewidth
tAHRD
DS (pin RD)
AS (pin ALE) tRWS tRWH
R/W (pin WR)
Interface for data acquisition and control (for multi-standard teletext systems)
29
tASL tAHL tDW D IN tAHL (1) tASL tRD D OUT tDR tWD
(1) ALE, CS, RD, WR and DB7 to DB0
MGH085
CS
write cycle
BUS
read cycle
BUS
Product specification
SAA5250
Fig.12 Timing diagram for microcontroller interface (Motorola).
January 1987
handbook, full pagewidth
Philips Semiconductors
character period
DCK tWEL tWEW tWEH
WE tMSH tMSW
Interface for data acquisition and control (for multi-standard teletext systems)
30
tMSL tAV WRITE ADDRESS READ ADDRESS tMSL tDWL tAD DATA IN tDWH DATA OUT
MS
tAV
A10 to A0
WRITE ADDRESS
D7 to D0
DATA OUT
MGH086
Product specification
SAA5250
Fig.13 Timing diagram for memory interface.
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
handbook, full pagewidth
tDCKL DCK tDCKH SD
tSSD VAL IN/ SYNC tSVALI
tHSD
tHVALI
MGH079
Fig.14 Timing diagram for demodulator interface.
handbook, full pagewidth
VAL, CBB
DCK
VAL IN / SYNC
SD
CLOCK SYNCHRONIZATION BITS tDVAL
FRAMING CODE tWVAL
PREFIX AND DATA BYTES
VAL OUT
tWCBB CBB
MGH078
Fig.15 Timing diagram for all other I/O signals.
January 1987
31
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
PACKAGE OUTLINES DIP40: plastic dual in-line package; 40 leads (600 mil)
SAA5250
SOT129-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 40 21 MH wM (e 1)
pin 1 index E
1
20
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 4.0 0.16 b 1.70 1.14 0.067 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 15.24 0.60
L 3.60 3.05 0.14 0.12
ME 15.80 15.24 0.62 0.60
MH 17.42 15.90 0.69 0.63
w 0.254 0.01
Z (1) max. 2.25 0.089
52.50 51.50 2.067 2.028
14.1 13.7 0.56 0.54
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT129-1 REFERENCES IEC 051G08 JEDEC MO-015AJ EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-14
January 1987
32
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SAA5250
VSO40: plastic very small outline package; 40 leads
SOT158-1
D
E
A X
c y HE vMA
Z 40 21
Q A2 A1 pin 1 index Lp L 1 e bp 20 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.70 0.11 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 bp 0.42 0.30 c 0.22 0.14 D (1) 15.6 15.2 E (2) 7.6 7.5 0.30 0.29 e 0.762 0.03 HE 12.3 11.8 0.48 0.46 L 2.25 Lp 1.7 1.5 Q 1.15 1.05 v 0.2 w 0.1 y 0.1 Z (1) 0.6 0.3
0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60
0.067 0.089 0.059
0.045 0.024 0.008 0.004 0.004 0.041 0.012
7o 0o
Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT158-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-24
January 1987
33
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO and VSO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO and VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
SAA5250
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO and VSO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
January 1987
34
Philips Semiconductors
Product specification
Interface for data acquisition and control (for multi-standard teletext systems)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5250
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
January 1987
35

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